1. Field of the Invention
The present invention relates to a semiconductor storage device that precharges/discharges a bit line to read data from a memory cell.
2. Description of the Related Art
As described in, for example, PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003, R. MICHELONI et al. “The Flash Memory Read Path: Building Blocks and Critical Aspects” pp. 537-553 (see FIG. 6(a)), in a read operation performed by a semiconductor storage device such as a flash memory, a power supply VDD first passes a current through a bit line via a resistor R. Then, the bit line is precharged to a predetermined level. On this occasion, when a memory cell (cell transistor) is on, the bit line is discharged. Accordingly, a sense amplifier senses the level of a node OUT to determine that the memory cell is on. On the other hand, when the memory cell is off, the level of the precharged bit line and node OUT is retained. Thus, the sense amplifier senses the level to determine that the memory cell is off.
With this read system, the precharge level of the bit line is adjusted by controlling a bias voltage BIAS applied to a gate of a MOS transistor M1. If the bias voltage BIAS is at the level of the power supply voltage VDD, the bit line is clamped to a level VDD-Vth (a threshold voltage of the MOS transistor M1). If the charge level of the bit line is excessively high, when the bit line has a large capacitance and the memory cell has only a small current, a long time is required to discharge the memory cell in the on state to a determination level. Further, to input a level equal to or lower than the power supply voltage VDD as the bias voltage BIAS to reduce the charge level of the bit line, a circuit is required which generates a bias voltage equal to or lower than VDD.
FIG. 7(b) in the above article describes, as another read circuit, a circuit in which an inverter carries out negative feedback to suppress excessive charging of the bit line. When a node A2 is at ground potential GND, the bias voltage BIAS supplied to the gate of the MOS transistor M1 is set at the VDD level to rapidly charge the bit line. Once the bit line is sufficiently precharged to, for example, about VDD/2, an output from the inverter is inverted to perform control such that the MOS transistor M1 is turned off. This makes it possible to suppress the excessive charging of the bit line.
This circuit configuration eliminates the need to apply a special voltage to the gate of the MOS transistor M1. Further, the level of the bit line is sensed so that the inverter can control the MOS transistor M1. Consequently, the circuit is simple.
However, since the inverter controls the precharge level of the bit line, a drain of the MOS transistor M1 has a voltage equal to or higher than the bit line voltage and equal to or lower than the power supply voltage VDD. Accordingly, after precharging, the charge on the drain of the MOS transistor M1 migrates to the bit line. As a result, the bit line is continuously charged weakly. This charging does not affect reading from the memory cell in an off state. However, when the bit line is discharged with the memory cell in the on state, the output from the inverter changes so that the MOS transistor M1 is turned on. Consequently, the charge on the drain of the MOS transistor M1 further charges the bit line. This operation charges the bit line being discharged by the memory cell in the on state. This is a factor delaying the operation of reading from the memory cell in the on state.
Further, the inverter need not operate for practical use while the bit line is being discharged. However, an input to the inverter is at an intermediate level between 0 V and VDD after the end of the read operation and before the potential across the bit line is reset to ground potential GND. Thus, during the read operation, the inverter continues to pass a through current. The through current is useless current consumption that is not related to operations.